インテル® VTune™ Amplifier 2018 ヘルプ
CPU Metrics Reference
Assists
Available Core Time
Average CPU Usage
Average Latency (cycles)
Average Loop Trip Count
Back-End Bound
BACLEARS
Bad Speculation (Cancelled Pipeline Slots)
Bad Speculation (Back-End Bound Pipeline Slots)
Branch Mispredict
Bus Lock
Cache Bound
Clockticks per Instructions Retired (CPI)
Clockticks Vs. Pipeline Slots Based Metrics
CPI Rate
CPI Rate (Intel® Atom™ processor)
CPU Time
Core Bound
Core Frequency
CPU Frequency Ratio
CPU Time
CPU Usage
CPU Utilization
CPU Utilization (OpenMP)
Cycles of 0 Ports Utilized
Cycles of 1 Port Utilized
Cycles of 2 Ports Utilized
Cycles of 3+ Ports Utilized
Divider
DRAM Bandwidth Bound
DRAM Bound
(Info) DSB Coverage
DTLB Store Overhead
Effective Time
Elapsed Time
Elapsed Time
Elapsed Time
Estimated BB Execution Count
Estimated Call Count
Estimated Ideal Time
Execution Stalls
False Sharing
Far Branch
Flags Merge Stalls
FPU Utilization
Front-End Bandwidth
Front-End Bandwidth DSB
Front-End Bandwidth LSD
Front-End Bandwidth MITE
Front-End Bound
Front-End Latency
General Retirement
Hardware Event Count
Hardware Event Sample Count
ICache Line Fetch
Ideal Time
Imbalance or Serial Spinning
Inactive Time
Instruction Starvation
Interrupt Time
I/O Wait Time
IPC
L1 Bound
L1 Hit Rate
L1D Replacement Percentage
L1D Replacements
L1I Stall Cycles
L2 Bound
L2 Hit Bound
L2 Hit Rate
L2 Miss Bound
L2 Miss Count
L2 Replacement Percentage
L2 Replacements
L3 Bound
LLC Load Misses Serviced By Remote DRAM
LLC Miss Count
LLC Replacement Percentage
LLC Replacements
Local DRAM
Local DRAM Access Count
Loop Entry Count
(Info) LSD Coverage
Machine Clears
Max DRAM Single-Package Bandwidth
Max DRAM System Bandwidth
MCDRAM Bandwidth Bound
MCDRAM Cache Bandwidth Bound
MCDRAM Flat Bandwidth Bound
Memory Bandwidth
Memory Bound
Memory Bus Transactions
Memory Efficiency
Memory Latency
Microcode Sequencer
MO Machine Clear Overhead
MPI Imbalance
MPI Rank on the Critical Path
MS Entry
MUX Reliability
NUMA: % of Remote Accesses
OpenMP* Analysis. Collection Time
Page Walk
OpenMP* Potential Gain
OpenMP Region Time
Other
Overhead Time
Parallel Region Time
Paused Time
Pipeline Slots
Precise Clockticks
Pre-Decode Wrong
Remote Cache
Remote Cache Access Count
Remote DRAM
Remote DRAM Access Count
Remote / Local DRAM Ratio
Retire Stalls
Retiring
Self Time and Total Time
Serial CPU Time
Serial Time (outside parallel regions)
SIMD Assists
SIMD Compute-to-L1 Access Ratio
SIMD Compute-to-L2 Access Ratio
SIMD Instructions per Cycle
Slow LEA Stalls
SMC Machine Clear
SP FLOPs per Cycle
SP GFLOPS
Spin Time
Spin and Overhead Time
Split Stores
Store Bound
Store Latency
Task Time
Thread Concurrency
Thread Oversubscription
Total Iteration Count
[uOps]
VPU Utilization
Wait Count
Wait Rate
Wait Time